`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:40:29 03/28/2013
// Design Name:   clock_divider
// Module Name:   C:/ASU/CSE320/Project2/tb/tb_clock_divider.v
// Project Name:  Project2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: clock_divider
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_clock_divider;

	// Inputs
	reg reset;
	reg clk_in;

	// Outputs
	wire clk_out;

	// Instantiate the Unit Under Test (UUT)
	clock_divider uut (
		.reset(reset), 
		.clk_in(clk_in), 
		.clk_out(clk_out)
	);

	initial begin
		// Initialize Inputs
		reset = 0;
		clk_in = 0;
		forever #20 clk_in <= !clk_in;
		// Wait 100 ns for global reset to finish
		end
		initial
		begin
		
		#10;
		@(posedge clk_in) reset = 0;
		@(posedge clk_in) reset = 0;
		@(posedge clk_in) reset = 0;
		@(posedge clk_in) reset = 1;
		@(posedge clk_in) reset = 1;
		@(posedge clk_in) reset = 1;
		@(posedge clk_in) reset = 1;
		@(posedge clk_in) reset = 1;
		@(posedge clk_in) reset = 1;
		@(posedge clk_in) reset = 1;
		@(posedge clk_in) reset = 1;
		@(posedge clk_in) reset = 1;
      #500;
		$stop;
		// Add stimulus here

	end
	
	
      
endmodule

